Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs

Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these modelling factors on accuracy and performance is demonstrated by comparing GliPS to other tools on circuit-level and a simple toggle count based power simulator TPS on gate level.

• Type: Conference
• Year: 1998
• Where: DATE
• Authors: Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebel, Carl von Ossietzky
• Keywords: DATE 1998, Hardware, Power Simulator, Power Simulator Tps, Power-simulation Tool Glips