Fine Grain Incremental Rescheduling Via Architectural Retiming

With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact on delay and area. The need thus arises for developing techniques and tools to redesign incrementally to eliminate performance bottlenecks. Such a redesign e ort corresponds to incrementally modifying an existing schedule obtained via high-level synthesis. In this paper we demonstrate that applying architecturalretiming, a techniquefor pipelininglatencyconstrained circuits, results in incrementally modifying an existingschedule. Architecturalretiming reschedules ne grain operations ones that have a delay equal to or less than one clock cycle to occur in earlier time steps, while modifying the design to preserve its correctness.

• Type: Conference
• Year: 1998
• Where: ISSS
• Authors: Soha Hassoun
• Keywords: Hardware, Interconnect Delay, ISSS 1998, Reschedules Ne Grain, Techniquefor Pipelininglatencyconstrained Circuits