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ASPDAC
1998
ACM
79views Hardware» more  ASPDAC 1998»
14 years 3 months ago
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
Jiang-An He, Hideaki Kobayashi
ISSS
1998
IEEE
96views Hardware» more  ISSS 1998»
14 years 3 months ago
Fine Grain Incremental Rescheduling Via Architectural Retiming
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
Soha Hassoun
SLIP
2006
ACM
14 years 5 months ago
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk ...
Andrew B. Kahng, Bao Liu, Xu Xu
ISQED
2009
IEEE
94views Hardware» more  ISQED 2009»
14 years 6 months ago
Simultaneous buffer and interlayer via planning for 3D floorplanning
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong