Experimental Results for IDDQ and VLV Testing

An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed the Stage 1 tests were packaged for further investigation. This paper describes the experimental setup and the preliminary results for the final package test. We focus on the correlation among various defect classes, including IDDQ failures, Very-Low-Voltage (VLV) failures, timing-independent combinational (TIC) defects, and nonTIC defects. We used 2 supply voltages for VLV tests. Two test speeds were used at each supply voltage. 9 dies failed only the VLV Boolean tests, and 7 of these were confirmed to have had high IDDQ measurement results. We also investigated the defect classes of the test escapes for 100% single stuck fault (SSF), transition fault, and IDDQ test sets.

• Type: Conference
• Year: 1998
• Where: VTS
• Authors: Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey
• Keywords: Defect Classes, Final Package Test, Hardware, Supply Voltage, VTS 1998