A unified approach in the analysis of latches and flip-flops for low-power systems

In this paper we propose a set of rules for consistent estimation of the real performance and power features of the latch and flip-flop structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative latches and flipflops illustrate the advantages of our approach and the suitability of different design styles for low-power and highperformance applications. Keywords Master-Slave latch, flip-flop, power measurement, timing, optimization

• Type: Conference
• Year: 1998
• Where: ISLPED
• Authors: Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa
• Keywords: Certain Misleading Parameters, Hardware, ISLPED 1998, Power Budget Issues, Power Consumption Bottlenecks