Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders

This paper presents an in-depth case study in highperformance asynchronous adder design. A recent method, called “speculative completion”, is used. This method uses single-rail bundled datapaths but also allows early completion. Five new dynamic designs are presented for BrentKung and Carry-Bypass adders. Furthermore, two new architectures are introduced, which target (i) small number addition,and (ii)hybrid operation. Initial SPICEsimulation and statistical analysis show performance improvements up to 19% on random inputs and 14% on actual programs for 32-bit adders, and up to 29% on random inputs for 64-bit adders, over comparable synchronous designs.

• Type: Conference
• Year: 1997
• Where: ASYNC
• Authors: Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel
• Keywords: 64-bit Adders, ASYNC 1997, Carry-Bypass Adders, Hardware, Random Inputs