MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI provides assertions that certain register values are dead, meaning they will n...
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
MICRO
1997
IEEE
14 years 4 months ago
1997
IEEE
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces commo...