VTS
1997
IEEE
14 years 4 months ago
1997
IEEE
VTS
1997
IEEE
14 years 4 months ago
1997
IEEE
Despite all of the advantages that circular BIST ofsers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has se...
VTS
1997
IEEE
14 years 4 months ago
1997
IEEE
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
VTS
1997
IEEE
14 years 4 months ago
1997
IEEE
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
VTS
1997
IEEE
14 years 4 months ago
1997
IEEE
We address the problem of rectifying an incorrect combinational circuit against a given specification. Based on the symbolic BDD techniques, we consider the rectification process,...
VTS
1997
IEEE
14 years 4 months ago
1997
IEEE
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
VTS
1997
IEEE
14 years 4 months ago
1997
IEEE
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
VTS
1997
IEEE
14 years 4 months ago
1997
IEEE
A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a...
VTS
1997
IEEE
14 years 4 months ago
1997
IEEE