A Novel Universal Sequencer Hardware

This paper introduces a powerful novel sequencer hardware for controlling computational machines and for structured DMA (direct memory access) applications. The paper introduces the principles and the design of a novel class of this sequencer hardware which supports two-dimensional memory address space or at least the two-dimensional visualization of the traditional one-dimensional address space. From these concepts it derives a classification scheme of computational sequencing patterns and storage schemes.

• Type: Conference
• Year: 1997
• Where: ARCS
• Authors: Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
• Keywords: Address Space, ARCS 1997, Sequencer Hardware, Software Engineering, Two-dimensional Memory Address