Functional Verification Methodology of Chameleon Processor

- Functional verification of the new generation microprocessor developed by SGS-THOMSON Microelectronics makes extensive use of advanced technologies. This paper presents a global overview of the methodology and focuses on three main aspects : - Use of acceleration and emulation technologies for the verification of the VHDL specification in the early stages of the design. - Development and use of sequential verification methods built upon a commercially available formal proof tool. - Extensive use of combinational proof for circuit-level tion, in conjunction with transistor abstraction.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Françoise Casaubieilh, Anthony McIsaac, Mike Benjamin, Mike Bartley, François Pogodalla, Frédéric Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gérard Mas, Geoff Barrett, Christian Berthet
• Keywords: Available Formal Proof, Computer Architecture, DAC 1996, Functional Verification, Sequential Verification Methods