iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips

In this paper, we present the rst chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specied input signal patterns, and thermal boundary conditions, it automatically nds the CMOS on-chip steadystate temperature prole and the resulting circuit performance. iCET has been tested on several circuits and it can eciently analyze layouts containing tens of thousands of transistors on a desktop workstation.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang
• Keywords: Chip-level Electrothermal Simulator, CMOS On-chip Steadystate, Computer Architecture, DAC 1996, Input Signal Patterns