Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design

In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper have minimum depth. We show (1) any decomposition leads to a smaller or equal mapping depth regardless the decomposition algorithm used, and (2) the problem is NP-hard for unbounded networks when K 3 and remains NP-hard for K-bounded networks when K 5. We propose a gate decomposition algorithm, named DOGMA, which combines level-driven node packing technique (Chortle-d) and the network flow based optimal labeling technique (FlowMap). Experimental results show that networks decomposed by DOGMA allow depthoptimal technology mappers to improve the mapping solutions by up to 11% in depth and up to 35% in area comparing to the mapping results of networks decomposed by other existing decomposition algorithms.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Jason Cong, Yean-Yow Hwang
• Keywords: Computer Architecture, DAC 1996, Decomposition Algorithms, K-bounded Networks, LUT Mapping Solutions