Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor

Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing to its flexibility for verifying at many points during the design cycle. A unique "verification backplane" makes continuous tion at any level(s) of abstraction available to each design team member throughout the design cycle.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Val Popescu, Bill McNamara
• Keywords: Computer Architecture, DAC 1996, Design Cycle, Narrow Market Windows, Superscalar Processor Developers