An accurate LNS arithmetic unit using interleaved memory function interpolator

This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage requirements by allowing each stored function value to be used in interpolation across several segments. This strategy can be shown to always usefewer words of memory than an optimized polynomial with stored polynomial coeficients. Many accuracy requirements for the LNS arithmetic unit are possible. Although a round to nearest would be desirable, is cannot be easily achieved. The goal suggested here is to insure that the worst case LNS relative error is smaller than the worst cuse FP relative error. Using the interleaved memory interpolator, the detailed design of an LNS arithmetic unit is performed using a second order polynomial interpolator including approximately 91K bits of ROM.

• Type: Conference
• Year: 1993
• Where: ARITH
• Authors: David M. Lewis
• Keywords: Applied Computing, ARITH 1993, Interleaved Memory, LNS Arithmetic Unit, Polynomial