Modeling shared variables in VHDL

A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing such shared variables in VHDL, depending on the acceptable constraints on accesses to the variables. Also a set of guidelines for handling atomic updates of multiple shared variables is given.

• Type: Conference
• Year: 1994
• Where: EURODAC
• Authors: Jan Madsen, Jens P. Brage
• Keywords: Concurrent Processes, EURODAC 1994, Multiple Shared Variables, Shared Variables, VHDL