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31

EURODAC
1994
IEEE

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Design automation of self checking circuits

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Design automation of self checking circuits

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In this paper we explain the steps of the CAD tools developed for self checking circuits. The CAD tools developed are used to design Strongly Fault Secure, Strongly Code Disjoint (SFS/SCD) and Totally Self Checking, Code Disjoint (TSC/CD) circuits. Self checking combinatorial and sequential synchronous circuits including shift registers, counters, adders and checkers are designed, using these tools. The output of these CAD tools is given in structural level VHDL which can be synthesized via commercial tools. Key words: Design Automation, CAD, Totally Self Checking Circuits, Strongly Fault Secure Circuits, VHDL.

Sayed Mohammad Kia, Sri Parameswaran

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Added	08 Aug 2010
Updated	08 Aug 2010
Type	Conference
Year	1994
Where	EURODAC
Authors	Sayed Mohammad Kia, Sri Parameswaran

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