Multi-way VLSI circuit partitioning based on dual net representation

In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propose a general paradigm for multi-way circuit partitioning based on dual net transformation. Given a netlist we first compute a K-way partitioning of nets based on the HDN representation, and then transform the K-way net partition into a K-way module partitioning solution. The main contribution of our work is in the formulation and solution of the K-way module contention (K-MC) problem, which determines the best assignment of the modules in contention to partitions while maintaining user-specified area requirements, when we transform the net partition into a module partition. Under a natural definition of binding factor between nets and modules, and preference function between partitions and modules, we show that the K-MC problem can be reduced to a min-cost max-flow problem. We present an efficient solution to...

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Jason Cong, Wilburt Labio, Narayanan Shivakumar
• Keywords: Dual Netlist, Hardware, ICCAD 1994, Multi-way Partitioning Problem, Net Partition