Mesh Routing Topologies for Multi-FPGA Systems

There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce inter-chip delays by more than 60% over the basic 4-way Mesh.

• Type: Conference
• Year: 1994
• Where: ICCD
• Authors: Scott Hauck, Gaetano Borriello, Carl Ebeling
• Keywords: Basic 4-way Mesh, Hardware, ICCD 1994, Mesh Interconnection Schemes, Proper Routing Topology