Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications

This paper presents a new method,based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expected number of clock cycles required by the schedule for a complete execution of the behavioral specification for any distribution of inputs. The measure considers both the repetition of operations (due to loops) and their conditional execution (due to conditional branches). We propose an efficient technique to calculate the metric. We introduce a loop-directed scheduling algorithm (LDS). The algorithm produces schedules such that the expected number of clock cycles, required by the schedule for a complete execution of the behavioral specification, is minimized. Experimental results on several conditional and loop-intensive specifications demonstrate the relevance and effectiveness of both the performance measure and the scheduling algorithm.

• Type: Conference
• Year: 1994
• Where: DAC
• Authors: Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
• Keywords: Behavioral Specification, Clock Cycles, Computer Architecture, DAC 1994, Performance Measure