Clock Grouping: A Low Cost DFT Methodology for Delay Testing

A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault coverage for circuits by exercising greater control over ip- op clocks in the test mode. In the test mode, the ip- ops are partitioned into dierent clock-groups. The ip- ops in each clock group can be either clocked or not clocked, independent of the ip- ops in the other groups. This exibility is used to enhance the number of dierent (v1; v2) test pairs that can be applied to the state inputs of the circuit thereby increasing coverage of delay faults. Experimental data on benchmark circuits shows that high fault coverage can be obtained by using only two clock groups in most circuits. The proposed clock grouping methodology can be applied to non-scan circuits as well. In fact, it can provide a DFT solution for high speed data path circuits where the performance penalties ofconventionalDFT techniques are un...

• Type: Conference
• Year: 1994
• Where: DAC
• Authors: Wen-Chang Fang, Sandeep K. Gupta
• Keywords: Computer Architecture, DAC 1994, Delay Fault Coverage, Delay Faults, Sequential Synchronous Circuits