Minimal Delay Interconnect Design Using Alphabetic Trees

Abstract - We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner and does not greedily add edges as in conventional approaches. The algorithm can handle cases where the sink capacitances are different. Good results are obtained while running two to sixty times faster than three existing algorithms on practical instances.

• Type: Conference
• Year: 1994
• Where: DAC
• Authors: Ashok Vittal, Malgorzata Marek-Sadowska
• Keywords: Algorithms, Computer Architecture, DAC 1994, Interconnect Design Problem, Interconnect Topology