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    Formal Verification of Digital Circuits Using Symbolic Ternary System Models

    14 years 4 months ago
    Formal Verification of Digital Circuits Using Symbolic Ternary System Models
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    Ternary system modeling involves extending the traditional set of binary values
    Randal E. Bryant, Carl-Johan H. Seger
    claim paper
    Added 10 Aug 2010
    Updated 10 Aug 2010
    Type Conference
    Year 1990
    Where CAV
    Authors Randal E. Bryant, Carl-Johan H. Seger
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