Floorplanning with Pin Assignment

We present a hierarchicaltechniquefor floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the extemal 110pads and upper bound delay constraintsfor a set of criticalnets, we determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnectionlength and constraintviolations for critical nets is minimized. Floorplanning,pin assignment and global routinginfluenceone anotherduring the hierarchicalsteps of the algorithm. The pin assignmentalgorithm is flexible and allows various user specified constraintssuch as pre-specified pin locations, feedthroughpins,length-criticalnets and planarnet topologies.Placement, timing and floorplanningresults for Xerox general cell benchmark are reported.

• Type: Conference
• Year: 1990
• Where: ICCAD
• Authors: Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh
• Keywords: General Cell, General Cell Layouts, Hardware, ICCAD 1990, Pin Assignment