Fast Electrical Correction Using Resizing and Buffering

Current design methodologies are geared towards meeting different design criteria, such as delay, area or power. However, in order to correctly identify the critical parts of a circuit for optimization, the circuit has to be electrically clean

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud
• Keywords: ASPDAC 2007, Current Design Methodologies, Electrical Violation, Electrical Violation Eliminator, Hardware