A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks

How to estimate the shortest routing length when certain blocks are considered as routing obstacles is becoming an essential problem for block placement because HPWL is no longer valid in this case. Although this problem is well studied in computational geometry [6], the research results are neither well-known to the CAD community nor presented in a way easy for CAD researchers to ultilize their establishment. With the help of some recent notions in block placement, this paper interprets the research result in [1,8], which gives the best algorithm for this problem as we know, in a way more concise and more friendly to CAD researchers. Besides, we also tailor its algorithm to VLSI CAD application. As the result, we present a method that estimates the shortest obstacle-avoiding routing length in time for a placement with blocks and 2-pin nets.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Tan Yan, Shuting Li, Yasuhiro Takashima, H. Murata
• Keywords: ASPDAC 2007, Block Placement, CAD Researchers, Hardware, Routing Length