Fast Placement Optimization of Power Supply Pads

Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of power pads that minimize not only the worst voltage drop but also the voltage deviation across the power grid. Our algorithm uses simulated annealing to minimize the total cost of voltage drops. The key enabler for efficient optimization is a fast localized node-based iterative method to compute the voltages after each movement of pads. Experimental results show that our algorithm demonstrates good runtime characteristics for power grids with large numbers of pad candidates in multi-million-size circuits. For a 16-million-node power grid with 646 thousand pad candidates, our algorithm took 72 minutes to improve the worst voltage drop from to and reduce the deviation of voltages on the power grid from to .

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Yu Zhong, Martin D. F. Wong
• Keywords: ASPDAC 2007, Hardware, Power Grid, Voltage Drop, Worst Voltage Drop