Design Methodology for 2.4GHz Dual-Core Microprocessor

This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64TM microprocessor with 90nm CMOS technology. It focuses on the newly adopted techniques, such as efficient data management in dual-core design, fast delay calculation of the noise-immune clock distribution circuit, enhanced signal integrity analysis of a large-scale custom macro design, and enhanced diagnosis capability using a logic BIST circuit.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda
• Keywords: ASPDAC 2007, Dual-core Design, Dual-core Sparc64tm Microprocessor, Hardware, Logic Bist Circuit