Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms

We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system design is the widening gap between the memory demand generated by the processor cores and the limited off-chip memory bandwidth and memory service speed. This severely restricts the number of cores that can be integrated into a multi-core system and the parallelism that can be actually achieved and efficiently exploited for not only memory demanding applications, but also for workloads consisting of many tasks utilizing a large number of cores and thus exceeding the available off-chip bandwidth. Last level shared cache partitioning has been shown to be a promising technique to enhance cache utilization and reduce missrates. While most cache partitioning techniques focus on cache miss rates, our work takes a different approach in which tasks’ memory bandwidth requirements are taken into account when identi...

• Type: Conference
• Year: 2010
• Where: DAC
• Authors: Chenjie Yu, Peter Petrov
• Keywords: Cache Partitioning, Computer Architecture, DAC 2010, Memory Bandwidth, Off-chip Memory Bandwidth