Efficient hardware checkpointing: concepts, overhead analysis, and implementation

Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is an effective methodology to cope with faults. In this paper, we systematically extend the concept of checkpointing known from software systems to hardware tasks running on reconfigurable devices. We will classify different mechanisms for hardware checkpointing and present formulas for estimating the hardware overhead. Moreover, we will reveal a tool that takes over the burden of modifying hardware modules for checkpointing. Post-synthesis results of applying our methodology to different hardware accelerators will be presented and the results will be compared with the theoretical estimations. Categories and Subject Descriptors B.5.3 [Hardware]: Register-Transfer-Level ImplementationReliability and Testing[Redundant design] General Terms Design, Reliability Keywords Checkpointing, State Access

• Type: Conference
• Year: 2007
• Where: FPGA
• Authors: Dirk Koch, Christian Haubelt, Jürgen Teich
• Keywords: FPGA, FPGA 2007, Hardware, Hardware Checkpointing, Reconfigurable Hardware Technology