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    FPGA
    2007
    ACM
    124views FPGA» more  FPGA 2007»
    Efficient hardware checkpointing: concepts, overhead analysis, and implementation
    14 years 4 months ago
    Efficient hardware checkpointing: concepts, overhead analysis, and implementation
    Download  www12.informatik.uni-erlangen.de
    Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
    Dirk Koch, Christian Haubelt, Jürgen Teich
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    FPGA
    2007
    ACM
    124views FPGA» more  FPGA 2007»
    A practical FPGA-based framework for novel CMP research
    14 years 7 months ago
    A practical FPGA-based framework for novel CMP research
    Download  csl.stanford.edu
    Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
    Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy T...
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    FPGA
    2007
    ACM
    119views FPGA» more  FPGA 2007»
    Synthesis of an application-specific soft multiprocessor system
    14 years 7 months ago
    Synthesis of an application-specific soft multiprocessor system
    Download  cadlab.cs.ucla.edu
    The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
    Jason Cong, Guoling Han, Wei Jiang
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    FPGA
    2007
    ACM
    153views FPGA» more  FPGA 2007»
    Variation-aware routing for FPGAs
    14 years 7 months ago
    Variation-aware routing for FPGAs
    Download  www.gtcad.gatech.edu
    Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
    Satish Sivaswamy, Kia Bazargan
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    FPGA
    2007
    ACM
    150views FPGA» more  FPGA 2007»
    FPGA-friendly code compression for horizontal microcoded custom IPs
    14 years 7 months ago
    FPGA-friendly code compression for horizontal microcoded custom IPs
    Download  www.ics.uci.edu
    Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
    Bita Gorjiara, Daniel Gajski
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    FPGA
    2007
    ACM
    163views FPGA» more  FPGA 2007»
    Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
    14 years 7 months ago
    Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
    Download  cadlab.cs.ucla.edu
    Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
    Jason Cong, Kirill Minkovich
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    FPGA
    2007
    ACM
    185views FPGA» more  FPGA 2007»
    Power-aware FPGA logic synthesis using binary decision diagrams
    14 years 7 months ago
    Power-aware FPGA logic synthesis using binary decision diagrams
    Download  www.ecs.umass.edu
    Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
    Kevin Oo Tinmaung, David Howland, Russell Tessier
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    FPGA
    2007
    ACM
    106views FPGA» more  FPGA 2007»
    A synthesizable datapath-oriented embedded FPGA fabric
    14 years 7 months ago
    A synthesizable datapath-oriented embedded FPGA fabric
    Download  www.ece.ubc.ca
    We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
    Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai ...
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    FPGA
    2007
    ACM
    114views FPGA» more  FPGA 2007»
    Design of a logic element for implementing an asynchronous FPGA
    14 years 7 months ago
    Design of a logic element for implementing an asynchronous FPGA
    Download  comp.uark.edu
    A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including...
    Scott C. Smith
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    FPGA
    2007
    ACM
    122views FPGA» more  FPGA 2007»
    The shunt: an FPGA-based accelerator for network intrusion prevention
    14 years 7 months ago
    The shunt: an FPGA-based accelerator for network intrusion prevention
    Download  www.icsi.berkeley.edu
    Today’s network intrusion prevention systems (IPSs) must perform increasingly sophisticated analysis—parsing protocols and interpreting application dialogs rather than simply ...
    Nicholas Weaver, Vern Paxson, José M. Gonz&...
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