An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs

Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-time very much. The number of cuts exponentially increases with the size of cuts, which causes long runtime. Furthermore, an ineciency of bottom-up merging in existing algorithms makes the run-time much longer. This paper presents a novel cut enumeration. The proposed algorithm is ecient because it enumerates cuts without bottomup merging. Our algorithm has two modes; exhaustive enumeration and partial enumeration. Exhaustive enumeration enumerates all cuts. Partial enumeration enumerates partial cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that exhaustive enumeration runs about 3 times and 8 times faster than existing bottom-up algorithm [1] [2] for K = 8, 9, respectively. The quality of network are the same. Furthermore, partial enumeration runs about 6 t...

• Type: Conference
• Year: 2009
• Where: GLVLSI
• Authors: Taiga Takata, Yusuke Matsunaga
• Keywords: Cut Enumeration, Exhaustive Enumeration, GLVLSI 2009, Partial Enumeration, VLSI