Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper presents a novel flexible decoder architecture for irregular LDPC codes that supports twelve combinations of code lengths -648, 1296, 1944 bits- and code rates1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All the codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. A prototype of the LDPC decoder has been implemented and tested on a Xilinx FPGA and has been synthesized for ASIC.

• Type: Conference
• Year: 2006
• Where: ASAP
• Authors: Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro
• Keywords: ASAP 2006, Density Parity Check, Error Correcting Codes, Hardware, Parity Check