Fast exploration of bus-based on-chip communication architectures

As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks. It therefore becomes extremely important for designers to explore the communication space early in the design flow. Traditionally, pinaccurate Bus Cycle Accurate (PA-BCA) models were used for exploring the communication space. To speed up simulation, transaction based Bus Cycle Accurate (T-BCA) models have been proposed, which borrow concepts found in the Transaction Level Modeling (TLM) domain. More recently, the Cycle Count Accurate action Boundaries (CCATB) modeling abstraction was introduced for fast communication space exploration. In this paper, we describe the mechanisms that produce the speedup in CCATB models and demonstrate the effectiveness of the CCATB exploration approach with the aid of...

• Type: Conference
• Year: 2004
• Where: CODES
• Authors: Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
• Keywords: Bus Cycle, CODES 2004, Communication Space, Simulation Speedup Scales, Software Engineering