A Design Methodology for the Exploitation of High Level Communication Synthesis

In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In particular, the issues related to the synthesis of the communication between the system elements are considered. The context in which the analysis is performed is the design flow proposed in the ODETTE project: in this ambient, SystemC is exploited in order to provide efficient system-level models; after that, the SystemC+ SystemC subset and extensions can be used to get a refined description that, despite the use of object oriented features such as polymorphism and inheritance, can be automatically synthesised by means of the ODETTE tools. Still, the problem of interfacing the hardware synthesised with the other elements of the design (memories, peripherals) remains an important issue. In order to face this problem, we propose a pattern that can be used to design bus interfaces that allow both an high abstracti...

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Francesco Bruschi, Massimo Bombana
• Keywords: Automatic Synthesis, DATE 2004, Design Flow, Hardware, ODETTE Tools