Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor

ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current functional verification approaches. The paper reports on a large-scale experiment employing the CVE property checker for verifying the block-level functional correctness of a large ASIC. This new verification methodology achieves substantial quality and productivity gains. The two biggest advantages are:

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
• Keywords: DATE 2004, Formal Property Checking, Functional Verification, Hardware, Static Timing Analysis