Mixed Loopback BiST for RF Digital Transceivers

In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generator and response analyzer. The test is oriented at spot defects in a transceiver front-end. Estimates for noise, signal power and nonlinear distortions such as EVM (or SER), gain and IP3, respectively, are considered the test responses. Limitations of these tests are investigated with respect to the test path properties, the strength of defects and circuit tolerances. The IP3 test complements the EVM (SER) and gain tests for some spot defects. The analysis is verified by simulation of a functional-level RF transceiver model implemented in Matlab .

• Type: Conference
• Year: 2004
• Where: DFT
• Authors: Jerzy Dabrowski, Javier Gonzalez Bayon
• Keywords: DFT 2004, IC Digital Transceivers, Spot Defects, Test Pattern Generator, VLSI