Improvements to technology mapping for LUT-based FPGAs

The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new technique for on-the-fly cut dropping reduces by orders of magnitude memory needed to represent cuts for large designs. Improved area recovery leads to mappings with area on average 7% smaller than DAOmap, while preserving delay optimality when starting from the same optimized netlists. Applying mapping with structural choices derived by a synthesis flow on average reduces delay by 7% and area by 14%, compared to DAOmap. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids--Optimization; B.7.1 [Integrated Circuits]: Types and Design Styles--Gate arrays; J.6 [Computer-Aided Engineering]: Computeraided design (CAD) General Terms Algorithms Keywords FPGA, Technology Mapping, Cut...

• Type: Conference
• Year: 2006
• Where: FPGA
• Authors: Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
• Keywords: Cut Dropping Reduces, Cut Enumeration, FPGA, FPGA 2006, Technology Mapping