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ICCAD
1995
IEEE
113views Hardware» more  ICCAD 1995»
14 years 3 months ago
Logic decomposition during technology mapping
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
Eric Lehman, Yosinori Watanabe, Joel Grodstein, He...
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
14 years 3 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
14 years 3 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
FPL
1997
Springer
242views Hardware» more  FPL 1997»
14 years 3 months ago
Technology mapping by binate covering
Technology mapping can be viewed as the optimization problem of finding a minimum cost cover of the given Boolean network by choosing from given library of logic cells. The core of...
Michal Servít, Kang Yi
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
14 years 3 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
14 years 4 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong
ISPD
2004
ACM
92views Hardware» more  ISPD 2004»
14 years 5 months ago
A predictive distributed congestion metric and its application to technology mapping
Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for...
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant S...
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 5 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
DAC
2006
ACM
15 years 15 days ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong