A Congestion Driven Placement Algorithm for FPGA Synthesis

We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that compared with the linear congestion method [1] used in the state-of-the-art FPGA place and route package VPR [2], our algorithm achieves channel width reduction on 70% of the 20 largest MCNC benchmark circuits (10.1% on average) while keeping the channel width of the remaining 30% benchmarks unchanged. A distinct feature of our algorithm is that the critical path delay is not elongated on average, and in most cases reduced.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: Yue Zhuo, Hao Li, Saraju P. Mohanty
• Keywords: Algorithm Achieves Channel, Channel Width, Congestion Driven Placement, FPL 2006, Hardware