New timing and routability driven placement algorithms for FPGA synthesis

We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accurately, our algorithms simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of our algorithm consists of a criticalityhistory record of connection edges and a congestion map. This approach is applied to the 20 largest MCNC benchmark circuits. Experimental results show that compared with VPR [2], our algorithms yield an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of our algorithms is only 2.3X as of VPR’s. Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuit, Design Aids]: Placement and Routing General Terms Algorithms, Design, Performance, Congestion Keywords Timing Driven Placement, Congestion Driven Placement, Physical Synthesis, Net Weight

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
• Keywords: Algorithms, Congestion Driven Fpga, Critical Path Delay, GLVLSI 2007, VLSI