On-FPGA Communication Architectures and Design Factors

The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing power as well as opportunities for rapid system prototyping. These platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication. However, as the number of embedded processors increases, communication bandwidth between embedded components becomes a limiting factor to overall system performance. In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies. Salient factors, which include quantitative performance metrics and qualitative factors, relevant to design are identified and used to analyze and classify the on-FPGA communication architectures. This survey aims to facilitate innovation in and development of future on-FPGA communication architectures.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
• Keywords: Communication Architectures, FPL 2006, Hardware, On-chip Communication Architectures, On-FPGA Communication Architectures