Identifying FPGA IP-Cores Based on Lookup Table Content Analysis

In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP protection against unlicensed usage. We show methods to extract the content of the lookup tables in a design from a binary bitfile of Xilinx Virtex-II and Virtex-II Pro FPGAs. To identify a core, we compare the number of unique functions from lookup tables of the core with the lookup tables extracted from a product with an FPGA from an accused company. Also placement information can be used for increasing the reliability of the result. With these methods, no additional sources or information must be inquired from the accused company. These techniques can be used for netlist and bitfile cores, so a wide spectrum of cores can be identified.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: Daniel Ziener, Stefan Assmus, Jürgen Teich
• Keywords: Cores, FPL 2006, Hardware, IP Cores, Lookup Tables