On speeding up extended finite state machines using catalyst circuitry

We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical path often forms a cycle and thus cannot be cut down easily by popular techniques such as pipelining or retiming. The proposed technique, based on the concept of catalyst, adds a functionally redundant block

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Shi-Yu Huang
• Keywords: ASPDAC 2001, Complex Finite State, Hardware, Timing Critical Paths, Timing Optimization Technique