High-level specification and efficient implementation of pipelined circuits

This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Maria-Cristina V. Marinescu, Martin C. Rinard
• Keywords: ASPDAC 2001, Complex Pipelined Circuits, Efficient Implementation, Hardware, Modular Specification Language