High-level design for asynchronous logic

Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Level Design flow for asynchronous circuits based on Register Transfer Level (RTL) VHDL using commercial simulation and synthesis tools. Contrary to previous asynchronous approaches, the proposed RTL methodology closely resembles familiar synchronous design styles.

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Ross Smith, Michiel M. Ligthart
• Keywords: ASPDAC 2001, Asynchronous Circuits, Familiar Synchronous Design, Hardware, Level Design Flow