Framework of Timed Trace Theoretic Verification Revisited

This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.

• Type: Conference
• Year: 2001
• Where: ATS
• Authors: Bin Zhou, Tomohiro Yoneda, Chris J. Myers
• Keywords: ATS 2001, Hardware, Hierarchical Verification, Timed Circuits, Trace Theoretic Verification