ASYNC
1997
IEEE
14 years 3 months ago
1997
IEEE
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
ATS
2001
IEEE
14 years 3 months ago
2001
IEEE
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or...
VLSID
1999
IEEE
14 years 3 months ago
1999
IEEE
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
ATVA
2004
Springer
14 years 4 months ago
2004
Springer
This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits effic...