Technology mapping for k/m-macrocell based FPGAs

In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this architecture can implement a single output function of up to k inputs and up to m product terms. We develop a very efficient technology mapping algorithm, k_m_flow, for this new type of architecture. The experiment results show our algorithm can achieve depthoptimality in practically all cases. Furthermore it is shown that the k/m-macrocell based FPGAs are practically equivalent to the traditional k-LUT based FPGAs with only a relatively small number of product terms (mk+3). We also investigate the total area and delay of k/m-macrocell based FPGAs on various benchmarks to compare it with commonly used 4-LUT based FPGAs. The experimental result shows k/m-macrocell based FPGAs can outperform 4-LUT based FPGAs in terms of both delay and area after placement and routing by VPR.

• Type: Conference
• Year: 2000
• Where: FPGA
• Authors: Jason Cong, Hui Huang, Xin Yuan
• Keywords: 4-lut Based Fpgas, FPGA, FPGA 2000, FPGAs, K/m-macrocell Based Fpgas