Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler

Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of the VIRAM architecture from the perspective of compiler writers, describing some of the code generation problems that arise in VIRAM and their solutions in the VIRAM compiler. VIRAM is a single chip system designed primarily for multimedia. It combines vector processing with mixed logic and DRAM to achieve high performance with relatively low energy, area, and design complexity. The paper focuses on two aspects of the VIRAM compiler and architecture. The first problem is to take advantage of the on-chip bandwidth for memory-intensive applications, including those with non-contiguous or unpredictable memory access patterns. The second problem is to support that kinds of narrow data types that arise in media processing, including processing of 8 and 16-bit data.

• Type: Conference
• Year: 2000
• Where: IMS
• Authors: David Judd, Katherine A. Yelick, Christoforos E. Kozyrakis, David Martin, David A. Patterson
• Keywords: Hardware, Hardware Standpoint Fail, IMS 2000, Many Architectural Ideas, VIRAM Compiler