Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

33

EURODAC
1995
IEEE

favoriteEmaildiscussreport

126views VHDL» more EURODAC 1995»

Quality considerations in delay fault testing

14 years 2 months ago

Quality considerations in delay fault testing

Download www.cs.york.ac.uk

We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signicantly aect the actual delays, but which are not taken into account by the existing models used in testing. Our analysis questions the test quality oered by test generation procedures used so far.

Alicja Pierzynska, Slawomir Pilarski

Real-time Traffic

Delay Models | EURODAC 1995 | Test Generation Procedures | VHDL | VLSI Circuit Testing |

claim paper

Related Content

» On Structural vs Functional Testing for Delay Faults

» On theoretical and practical considerations of path selection for delay fault testing

» Delay Test Quality Evaluation Using Bounded Gate Delays

» Hardware Generation of Random Single Input Change Test Sequences

» A dynamic test compaction procedure for highquality path delay testing

» High Quality ATPG for Delay Defects

» Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults

» Warning Launch off Shift Tests for Delay Faults May Contribute to Test Escapes

» A Novel Lowoverhead Delay Testing Technique for Arbitrary TwoPattern Test Application

Post Info
More Details (n/a)

Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	EURODAC
Authors	Alicja Pierzynska, Slawomir Pilarski

Comments (0)