Quality considerations in delay fault testing

We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signicantly aect the actual delays, but which are not taken into account by the existing models used in testing. Our analysis questions the test quality oered by test generation procedures used so far.

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Alicja Pierzynska, Slawomir Pilarski
• Keywords: Delay Models, EURODAC 1995, Test Generation Procedures, VHDL, VLSI Circuit Testing